1. Field
This disclosure relates generally to an integrated circuit design and, more specifically, to techniques for electromigration stress mitigation in interconnects of an integrated circuit design.
2. Related Art
Electromigration (EM) refers to the transport of material that is caused by gradual movement of ions in a conductor due to momentum transfer between conducting electrons and diffusing metal atoms. In general, EM should be considered in applications where relatively high direct current densities are expected, such as in microelectronics and related structures. As structure sizes in integrated circuits (ICs) decrease, the practical significance of EM increases. EM first became of practical interest in the electronics field when the first ICs became commercially available. EM research in the IC field began at a time when metal interconnects in ICs were about 10 micrometers wide. Currently, IC interconnects are hundreds to tens of nanometers in width. EM decreases the reliability of ICs (chips) and can cause the eventual loss of connections or failure of a circuit.
Although EM damage ultimately results in failure of an affected IC, initial symptoms may include intermittent glitches that are challenging to diagnose. As some interconnects fail before other interconnects, a circuit may exhibit random errors that are indistinguishable from other failure mechanisms. In a laboratory setting, EM failure may be readily viewed with an electron microscope, as interconnect erosion leaves visual markers on metal layers of an IC. With increasing IC miniaturization the probability of IC failure due to EM increases, as both power density and current density increase as IC size decreases. In advanced semiconductor manufacturing processes, copper has replaced aluminum as the interconnect material of choice, as copper is intrinsically less susceptible to EM. In modern consumer electronic devices, ICs rarely fail due to EM effects, because proper semiconductor design practices incorporate the effects of EM into the IC layouts. That is, nearly all IC design houses use automated electronic design automation (EDA) tools to detect and correct EM problems at the transistor layout-level.
In general, the “Blech length” has been used to denote a length limit for an interconnect below which EM will not occur at a given current density. That is, any interconnect whose length is below the “Blech length” will not typically fail due to EM at lower current densities, but may fail at higher current densities. In general, an interconnect whose length is below the “Blech length” experiences a mechanical stress build-up that causes a reverse migration process that reduces or even compensates for material flow.